Operating Systems · Memory virtualization

TLBs and fast address translation

A small hardware cache of recent address translations, so paging doesn't cost a memory access on every access.

Also known as: translation lookaside buffer, TLB miss.

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• Paging: Splitting memory into fixed-size pages so a process's address space doesn't need to sit in one contiguous block.

Related topics

• Multi-level and inverted page tables: Multi-level and inverted page tables, ways to keep the translation structure itself from eating too much memory.